CSE
CSE
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Defense Event

Leveraging Processor Features for System Security

Zelalem Birhanu Aweke


 
Thursday, December 06, 2018
1:30pm - 3:30pm
3725 Beyster Building

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About the Event

Errors in hardware and software lead to vulnerabilities that can be exploited by attackers. Proposed exploit mitigation techniques can be broadly categorized into two: software-only techniques and techniques that propose specialized hardware extensions. Software-only techniques can be implemented on existing hardware, but typically suffer from impractically high overheads. On the other hand, specialized hardware extensions, while improving performance, are not scalable as adding new hardware extension for every vulnerability is impractical. In this dissertation, we propose adapting existing processor features to provide novel and low-overhead security solutions. We demonstrate this approach by applying it against two security problems: rowhammer attacks and memory corruption vulnerabilities.

In the first part of the dissertation, we show how hardware performance counters in modern processors can be used to detect rowhammer attacks. Our technique detects rowhammer attacks by monitoring for high locality memory accesses out of the last-level cache using hardware performance counters. The technique accurately detects rowhammer attacks with a low performance overhead and without requiring hardware modifications.

In the second part of the dissertation, we show how modern hardware features can be used to provide efficient memory safety. One component of memory safety that has become important in recent years is temporal memory safety. Temporal memory safety techniques are used to detect memory errors such as use-after-free errors. This dissertation proposes a temporal memory safety technique that takes advantage of pointer authentication hardware to significantly reduce the memory and runtime overhead of traditional temporal safety techniques. Providing complete memory safety on resource constrained devices is expensive, therefore we propose software-based fault isolation (sandboxing) as an efficient alternative to constrain attackers’ access to code and data in embedded systems. The last part of the dissertation shows how we can use a memory protection unit (MPU) hardware available in many embedded devices along with a small trusted runtime to build a low overhead sandboxing mechanism.

Additional Information

Sponsor(s): Todd Austin

Open to: Public